Traditional wired-OR signal transfer devices have been created using a static approach by incorporating resistors to pull-up (or pull-down) a bus line to an invalid state. However, when the bus line is pulled to a valid state, relatively high levels of current may be wasted because the competing pull-up resistors and pull-down transistors may provide a low resistance path between power supply potentials (e.g., Vdd and Vss). This wasted current can be reduced by increasing the resistance of the pull-up resistors, however, such an increase will typically result in a reduction in pull-up speed.
Dynamic wired-OR signal transfer devices have also been used and these devices typically use a clock signal to precharge a bus line. The precharge devices are then turned off and the logic is enabled. This dynamic approach may save power compared to the static approach, however, the total time for an individual transition (pull-up or pull-down) may only be half of a clock cycle. For long and heavily capacitive lines, half a clock cycle may not provide a sufficient amount of time for adequate pull-up or pull-down. Asynchronously timed signal transfer devices have also been used, however, such circuits may require that pull-up and pull-down transistors be simultaneously conductive which can lead to excessive power consumption.
Thus, notwithstanding the above-described wired-OR signal transfer devices, there continues to be a need for improved and highly reliable and efficient signal transfer devices which have excellent pull-up and/or pull-down capability and reduced power consumption requirements.